A memory system is typically triggered by an external clock signal. In general, during each cycle of the clock signal a memory system operation is completed, such as, for example, a read, a write or a NOOP (no-operation cycle, during which the memory remains idle). Clock cycles usually occur continuously and sequentially. Two well-known types of memory are single-port memory (SPM) and dual-port memory (DPM).
A SPM array may employ separate input and output data buses. The combination of independent input and output data buses is commonly referred to as a port. Each data bus (input and output) typically includes one line for each bit in a data word of the memory; the number of lines in the data buses is thus a function of a word size of the memory array. For a write operation, during each memory cycle a data word presented to the input data bus may be written into a selected memory location addressed within the memory array. For a read operation, during each memory cycle a data word may be read from a selected memory location addressed within the memory array and presented to the output bus. In the case of a NOOP, a memory cycle may be executed without instructing the memory to perform a read or a write operation. In alternative memory arrangements, a single common input/output (I/O) data bus may be used both to present data to the memory for writing and to retrieve data from the memory when reading. The common I/O data bus is also commonly referred to as a port. A SPM array, by definition, has one port.
A DPM array is characterized by having two access ports to the memory array; that is, it has two sets of input data buses and two sets of output data buses, or alternately, two common I/O data buses. Each set of input and output data buses, or each single I/O data bus, is commonly referred to as a port. Each port may access memory cells in the array through separate memory cell paths, or access the memory cells through the same memory cell path but with only one port accessing the memory cell during any given memory cycle.
Dual-port memory arrays traditionally offer a higher data throughput compared to single-port memory arrays since two memory accesses can be performed in a single clock cycle in a dual-port memory array. However, in order to implement a dual-port memory architecture, each memory cell in the dual-port memory array requires additional transistors. For example, one conventional dual-port memory cell includes eight transistors; four of the transistors are interconnected to form two cross-coupled inverters functioning as a primary storage element in the cell and the remaining transistors are connected to form two access paths in the cell. By comparison, a single-port memory cell typically requires six transistors; four of the transistors are interconnected to form two cross-coupled inverters functioning as a primary storage element in the cell (as in the dual-port memory cell) and the remaining transistors are connected to form a single access path in the cell. The six-transistor single-port memory cell typically consumes about half as much integrated circuit area as the eight-transistor dual-port memory cell, and is therefore preferred.
Accordingly, there exists a need for an improved memory architecture capable of providing the advantages of dual-port access but which does not suffer from one or more of the above-noted problems exhibited by conventional dual-port memory architectures.